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export ltspice nach eagle 4.1.xx
#1
@alle:
Hallo Spicemen, gibt es sowas, oder muss man das ganze schöne Layout aus der Simulation nochmal in eagle reinfriemeln um ein ordentliches Layout zu routen?
 
#2
Hi dude,

ich arbeite mit Target!3001 ABER vielleicht geht das auch bei Eagle.
Im LTspice unter Tools->Export Netlist
kannste die Schaltung quasi exportieren (in verschiedenen Netlist Formaten)

Bei mir im Target kann ich dann die Netlist importieren. Allerdings müssen
die entsprechenden Bauteile die verwendet werden bereits auf dem Schaltplan
liegen. Is ja klar, in der Netlist ist ja keine Info zur Bibliothek deiner
Bauteile.
Erleichert aber dennoch die Arbeit, je nach größe des Projekts.
Die Bauteile müssen (zumindest bei Target) nicht gleich benannt sein, man
wird gefragt, welches Bauteil lokal selektiert werden soll.

Vielleicht kannste mit der Info was anfangen.
 
#3
Vielen Dank, drweb!

@all: ich hoffe ihr habt den rutsch ohne grösseren aufprall überstanden.

vielen dank für die schnelle auskunft mrweb, bin am Ball.
Aber ich hatte gehofft, dass der gewürzte Adler wohl die erschwinglichste kombi von schwabbelgut ist.

ich dachte ich könnte Leidensgenossen zu finden die den Rechner ebenso trietzen - oder Rummi?
 
#4
Irgendwie bin ich schon gespannt ob da noch was kommt-
Anybody out There ?
keiner mit einer Lösung?

Wer traut sich?
-Oder frag ich hier so blöden Mist dass sich keiner hier die blösse geben will?
 
#5
Hi,

bin der Meinung das es da ein ULP bei CadSoft gibt.
Nur musst du erstmal die Bauteile auf dem Board Plazieren,
Name und Anzahl/Bezeichnung der Bauteile müssen gleich
sein.

Wenn du die Netzliste aus deinem Prog. als Text-Datei bekommst
kannst du die Netz-Liste auch einfach in Eagle einlesen.

Gruß
 
#6
Zitat:Original geschrieben von Bandre

Hi,

bin der Meinung das es da ein ULP bei CadSoft gibt.
Nur musst du erstmal die Bauteile auf dem Board Plazieren,
Name und Anzahl/Bezeichnung der Bauteile müssen gleich
sein.

Wenn du die Netzliste aus deinem Prog. als Text-Datei bekommst
kannst du die Netz-Liste auch einfach in Eagle einlesen.

Gruß

nabend zusammen...

nööö nich bei Cadsoft´s aber woanders...

los gehts...

/*----------------------------------------------------------------------------------------
SPICE Output of EAGLE Schematics with ULP
============================================

Load schematic name.sch and run ULP with

RUN spice

The SPICE netlist will be named name.cir.

The ULP generates for each part one line in the netlist.
Lines starting with "*" are comment.

Example Resistor:

R1 3 4 1Kohm
| |_| |
| | |_ Component value or model name (for complex components).
| | The value is defined with the VALUE command of EAGLE.
| | Must meet SPICE naming conventions!
| |
| |_ Node numbers between which the component is placed (they are equivalent to
| EAGLE nets in the schematic). The ULP transfers the net names to node numbers.
| Node 0 is always the reference node (ground); it is defined by the net GND
| in the schematic. Node numbers with a leading "-" character (e.g. -3) describe
| open pins - that is, the nets do not exist.
|
|_ Reference f. component category (in this case R for resistor). Is defined
with PREFIX in the EAGLE device. R1 is the complete component name defined
in the EAGLE schematic. For SPICE, only R is relevant. The name must
meet the SPICE conventions!

Example AND Gate:

U1 AND(2) $G_DPWR $G_DGND 3 -1 4 T_GATE_AND IO_STD ;7400
| |____________________| |____| |_______________| |___|__ EAGLE Value
| | | | (after ";" = comment)
| | | |
| | | |_ If instead of the value a more complex
| | | string is needed, this string is to be
| | | defined in the symbol( e.g. in layer SPICE).
| | | Here: "spicepostf T_GATE_AND IO_STD"
| | |
| | |_ Node numbers: The order must meet the demands of
| | the related SPICE model. It is equivalent to the
| | sort order (R1 before R10..) of the EAGLE pin names.
| | The order can be changed with the text:
| | "spiceorder Pinname1 Pinname2 Pinname3 .."
| | defined in the EAGLE-Symbol.
| | If less pins are specified in this text than the
| | symbol contains, nodes are generated only for those
| | pins.
| |
| |_ Some components need an additional string between name and node
| numbers. It is defined as text in the EAGLE symbol. Here:
| "spicepref AND(2) $G_DPWR $G_DGND"
|
|_ Component name according to SPICE conventions. "U" is defined as Prefix in the
EAGLE device. If SPICE needs a name different from the EAGLE component name,
the string "spicename X" can be placed in the EAGLE SPICE layer. "X" represents
a valid SPICE name and is preceeding the EAGLE component name.
Example:
EAGLE name: "IC1", string in layer SPICE: "spicename XAND", Spice-Name: "XANDIC1".


SPICE Strings
=============
The string in the layer SPICE should be small enough (size) not to extend the area
used by all the other objects of the EAGLE symbol, as the area is used in various
operations, even if the SPICE layer is not displayed.

Restrictions
============
Supply symbols (except GND) are ignored, as well as "gates" containing at least one
pin with Direction "Sup". Voltage sources are to be defined as a device.

Instruments etc.
================
Not only real components but also instruments, voltage sources, etc. can be defined
as EAGLE devices. These components must contain dummy packages and must not contain
pins with Direction "Sup".

Power Pins of Components
========================
If such pins are defined as an individual EAGLE "gate", they appear in the SPICE
netlist only if they have been expicitly placed in the schematic with the INVOKE
command. The naming of those "gates" however will lead to problems at the moment,
as for instance the name of the power gate belonging to component U1 will be U1xx
(if the gate name is xklappe.
----------------------------------------------------------------------------------------*/


/* Generate PSPICE netlist from EAGLE schematic */

string InsName = "",
PinName = "",
PinOrder,
PinSignals,
SpiceName = "spicename",
SpicePref = "spicepref",
SpicePostf = "spicepostf",
SpiceOrder = "spiceorder",
BeforeName,
BeforeNodes,
AfterNodes,
NodeOrder,
Nodes[];
int n,
i,
PinsNoNet,
t,
NrOfPins,
NrOfPinDefs,
PinOrderDefined;

string SignalOnPin (string InsName, string PinName)
{
string SigName = "";
schematic (Sch) {
Sch.nets(N){
N.pinrefs(PR) {
if (InsName == PR.instance.name)
if (PinName == PR.pin.name)
SigName = N.name;
}
};
return SigName;
}
}

string GetItemTillEnd(string s) { // check error handling yet
int i = 0;
while ((!isspace(s[i])) && (strlen(s) >= i))
i++; // skip first word
while ((isspace(s[i])) && (strlen(s) >= i))
i++; // skip blanks
s = strsub(s, i, strlen(s)-i);
return s;
}

string GetNextItem(string s) { // and stip NodeOrder
int i = 0;
string item = "";
if (strlen(s)) {
while (isspace(s[i])) {
i++; // skip first word
NodeOrder = strsub(NodeOrder, 1 , strlen(NodeOrder)-1);
}
while (isgraph(s[i])) {
item = item + s[i];
NodeOrder = strsub(NodeOrder, 1 , strlen(NodeOrder)-1);
i++;
};
};
return item;
}



void OutputPart_BB(UL_PART PRT) {
int IsSupplySymbol,
HasPins,
pos;
string s;
int padCount = 0;
UL_PACKAGE pkg;
pkg = PRT.device.package;

printf("\n");
PRT.instances(I) {
printf("\n( PartInstance (prop refname \"%s\") (prop devicename \"%s\") (prop gatename \"%s\")(prop topleft (POS %4d %4d))",
I.name, PRT.device.name, I.gate.name, I.x, I.y);
printf("(prop mirror %4d) (prop angle %4f)\n",
I.mirror, I.angle);
switch(I.gate.addlevel) {
case GATE_ADDLEVEL_MUST : printf(" (prop gateAddLevel must)"); break;
case GATE_ADDLEVEL_CAN : printf(" (prop gateAddLevel can)"); break;
case GATE_ADDLEVEL_NEXT: printf(" (prop gateAddLevel next)"); break;
case GATE_ADDLEVEL_REQUEST: printf(" (prop gateAddLevel request)"); break;
case GATE_ADDLEVEL_ALWAYS: printf(" (prop gateAddLevel always)"); break;
}
printf(" (prop value \"%s\") (prop sheet %d) \n", I.value, I.sheet);
if (PRT.device.package) {
printf("(prop packagename \"%s\") (prop library \"%s\")\n", PRT.device.package.name, PRT.device.package.library);
printf("(package ");
printf("(prop name \"%s\")\n",
PRT.device.package.name);
PRT.device.package.contacts© {
padCount++;
if (C.pad)
printf("(prop pad \"%s\") \n", C.pad.name);
if (C.smd)
printf("(prop pad \"%s\") \n", C.smd.name);
}
printf(")\n");
}
I.gate.symbol.pins(PIN) {
printf(" (pin (prop name \"%s\") (prop pos (POS %4d %4d)) (prop angle %f) ",
PIN.name, PIN.x, PIN.y, PIN.angle);
printf(" (prop swaplevel %4d)",
PIN.swaplevel);
switch(PIN.direction) {
case PIN_DIRECTION_NC: printf(" (prop direction NC)"); break;
case PIN_DIRECTION_IN: printf(" (prop direction IN)"); break;
case PIN_DIRECTION_OUT: printf(" (prop direction OUT)"); break;
case PIN_DIRECTION_IO: printf(" (prop direction IO)"); break;
case PIN_DIRECTION_OC: printf(" (prop direction OC)"); break;
case PIN_DIRECTION_PWR: printf(" (prop direction PWR)"); break;
case PIN_DIRECTION_PAS: printf(" (prop direction PAS)"); break;
case PIN_DIRECTION_HIZ: printf(" (prop direction HIZ)"); break;
case PIN_DIRECTION_SUP: printf(" (prop direction SUP)"); break;
}
switch(PIN.function) {
case PIN_FUNCTION_FLAG_NONE: printf(" (prop function NONE)"); break;
case PIN_FUNCTION_FLAG_DOT: printf(" (prop function DOT)"); break;
case PIN_FUNCTION_FLAG_CLK: printf(" (prop function CLK)"); break;
}
switch(PIN.length) {
case PIN_LENGTH_POINT: printf(" (prop length POINT)"); break;
case PIN_LENGTH_SHORT: printf(" (prop length SHORT)"); break;
case PIN_LENGTH_MIDDLE: printf(" (prop length MIDDLE)"); break;
case PIN_LENGTH_LONG: printf(" (prop length LONG)"); break;
}
switch(PIN.visible) {
case PIN_VISIBLE_FLAG_OFF: printf(" (prop visible OFF)"); break;
case PIN_VISIBLE_FLAG_PAD: printf(" (prop visible PAD)"); break;
case PIN_VISIBLE_FLAG_PIN: printf(" (prop visible PIN)"); break;
}
if (PRT.device.package)
if (PIN.contact)
printf(" (prop padname \"%s\")", PIN.contact.name);
printf(")\n");
PIN.circles(CIRCLE) {
printf(" (circle (prop layer %4d) (prop radius %4d) (prop center (POS %4d %4d)))\n",
CIRCLE.layer, CIRCLE.radius, CIRCLE.x, CIRCLE.y);
}
PIN.wires(W) {
if (!W.arc) {
printf(" (line (prop layer %4d) (prop width %4d) (prop x1 %4d)(prop y1 %4d) (prop x2 %4d)(prop y2 %4d))\n",
W.layer, W.width, W.x1, W.y1, W.x2, W.y2);
}
}
PIN.texts(T) {
printf(" (text (prop angle %4f) (prop layer %4d) (prop mirror %4d) (prop ratio %4d) (prop size %4d) (prop value \"%s\") (prop topleft (POS %4d %4d)))\n",
T.angle, T.layer, T.mirror, T.ratio, T.size, T.value, T.x, T.y);
}
}
I.gate.symbol.wires(ARC) {
if (ARC.arc) {
printf(" (arc (prop angle1 %4f) (prop angle2 %4f) (prop radius %4d) (prop width %4d) ",
ARC.arc.angle1, ARC.arc.angle2, ARC.arc.radius, ARC.arc.width);
printf(" (prop x1 %4d) (prop y1 %4d) (prop x2 %4d) (prop y2 %4d) (prop center (POS %4d %4d)))\n",
ARC.arc.x1, ARC.arc.y1, ARC.arc.x2, ARC.arc.y2, ARC.arc.xc, ARC.arc.yc);
}
}
I.gate.symbol.circles(CIRCLE) {
printf(" (circle (prop layer %4d) (prop radius %4d) (prop center (POS %4d %4d)))\n",
CIRCLE.layer, CIRCLE.radius, CIRCLE.x, CIRCLE.y);
}
I.gate.symbol.rectangles(RECT) {
printf(" (rect (prop layer %4d) (prop left %4d)(prop top %4d) (prop right %4d)(prop bottom %4d))\n",
RECT.layer, RECT.x1, RECT.y1, RECT.x2, RECT.y2);
}
I.gate.symbol.polygons(PGON) {
printf(" (polygon (prop isolate %4d) (prop layer %4d) (prop orphans %4d) (prop pour %4d)(prop spacing %4d) (prop thermals %4d)\n",
PGON.isolate, PGON.layer, PGON.orphans, PGON.pour, PGON.spacing, PGON.thermals);
PGON.wires(W) {
if (!W.arc) {
printf("(line (prop x1 %d) (prop y1 %d) (prop x2 %d) (prop y2 %d))\n",
W.x1, W.y1, W.x2, W.y2);
}
}
printf(")\n");
}
I.gate.symbol.texts(T) {
printf(" (text (prop angle %4f) (prop layer %4d) (prop mirror %4d) (prop ratio %4d) (prop size %4d) (prop value \"%s\") (prop topleft (POS %4d %4d)))\n",
T.angle, T.layer, T.mirror, T.ratio, T.size, T.value, T.x, T.y);
}
I.gate.symbol.wires(W) {
if (!W.arc) {
printf(" (line (prop layer %4d) (prop width %4d) (prop x1 %4d)(prop y1 %4d) (prop x2 %4d)(prop y2 %4d))\n",
W.layer, W.width, W.x1, W.y1, W.x2, W.y2);
}
}

printf(")\n");
}
}

if (schematic) schematic(SCH) {
t = time();
string fileName = dlgFileSave("Save File", filesetext(SCH.name, ".bdf"), "*.bdf");
if (fileName == "") exit(0);
output(fileName) {
n = 0;
SCH.nets(N) {
Nodes[0] = "GND";
if (N.name != "GND")
Nodes[++n] = N.name;
}
/* for (i = 0; i <= n; i++)
printf("* %4d %s\n", i, Nodes[i]);
printf("*\n");
*/
printf("(circuit \n");
PinsNoNet = 0;
SCH.sheets(SH){
printf("(Sheet (prop x1 %4d)(prop x2 %4d)(prop y1 %4d)(prop y2 %4d))\n",
SH.area.x1, SH.area.x2, SH.area.y1, SH.area.y2);
SH.parts(PRT)
OutputPart_BB(PRT);
}
SCH.sheets(SH) {
printf("(Sheet (prop x1 %4d)(prop x2 %4d)(prop y1 %4d)(prop y2 %4d))\n",
SH.area.x1, SH.area.x2, SH.area.y1, SH.area.y2);
SH.nets(N) {
printf("(Net (prop name \"%s\") (prop sheet %d)\n", N.name, SH.number);

N.segments(SEG){
printf("\t(Wire (prop name \"%s\") (prop sheet %d)\n", N.name, SH.number);

SEG.wires(W){

printf("\t\t(Segment (prop x1 %4d)(prop y1 %4d) (prop x2 %4d)(prop y2 %4d))\n", W.x1, W.y1, W.x2, W.y2);

}
SEG.pinrefs(P) {
printf("\t\t(pinref (prop refname \"%s\") (prop gatename %s) (prop pinname \"%s\") ",
P.instance.name, P.instance.gate.name, P.pin.name);
if (P.pin.contact)
printf(" (prop padname \"%s\")", P.pin.contact.name);
printf(")\n");
}
printf("\t)\n");
}
printf("\t\t)\n");
}
SH.busses(B) {
printf("(Bus (prop name \"%s\") (prop sheet %d)\n", B.name, SH.number);
B.segments(SEG){
printf("\t(Wire (prop name \"%s\") (prop sheet %d)\n", B.name, SH.number);
SEG.wires(W){
printf("\t\t(Segment (prop x1 %4d)(prop y1 %4d) (prop x2 %4d)(prop y2 %4d))\n", W.x1, W.y1, W.x2, W.y2);
}
SEG.pinrefs(P) {
printf("\t\t(pinref (prop refname \"%s\") (prop gatename \"%s\") (prop pinname \"%s\") ",
P.instance.name, P.instance.gate.name, P.pin.name);
if (P.pin.contact)
printf(" (prop padname \"%s\")", P.pin.contact.name);
printf(")\n");
}
printf("\t)\n");
}
printf("\t\t)\n");
}
}
printf(")");
}
}


//ende//

Gruss Adama