[zilog]

I have attached a .ASC to my UcD, it works but has much distortion (0.5%-ish), could somebody look at it and give me hints to where this distortion comes from? It also has problems with starting, and in some configurations it start/stops working in phase with the input signal.
It would also be nice if someone could help me with the calculations of feedback/lead network values as I dont understand putzey's equations well enough to discover values with other method than by random picking and simulating.

Kind Regards
Daniel Nilsson

https://stromrichter.org/d-amp/content/i...og_ucd.asc