[SSassen]

Okay, I'll do this in English, to avoid any confusion. I've modelled both my SODFA and UcD design in LTspice and the UcD is consistently generating better scores. Beobachter indicated that the carrier frequency is hard to control with a UcD design and he's right, yet I managed to lock it down to 400KHz on my UcD design without too much trouble. Below are the screenshots for both designs. They are run with the following commands:

SINE(0 x 10k) (x = 1 for UcD, 0.7 for SODFA)
.tran 0 500u 0 1u steady uic
.four 10kHz 10 V(OUTPUT)

Typical output for both designs is around 28vrms with 1vrms input into an 8-ohm load and both operate at 400KHz carrier frequency, give or take a few KHz. Below you'll also find the THD results clipped from the log files from both designs. I'll cut and paste the asc data in a second post as I do not want to make this post too lengthy.

In the below images you see in the top left corner the FFT result with 'none' selected for windowing. In the top right 'Hann' is selected for windowing. The magnification of the output is shown in the bottom left and you can clearly see the carrier frequency here.

ucd_class_d_002
[Bild: 11694.gif]

sodfa_class_d_001
[Bild: 11695.gif]

ucd_class_d_002 THD

Per .tran options, skipping operating point for transient analysis.
Changing Tseed to 1e-010
Changing Tseed to 1e-012
Heightened Def Con from 0.0005 to 0.0005
Fourier components of V(output)
DC component:0.173333

Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 1.000e+04 2.672e+01 1.000e+00 174.20° 0.00°
2 2.000e+04 8.681e-04 3.248e-05 109.55° -64.65°
3 3.000e+04 4.190e-03 1.568e-04 -36.04° -210.24°
4 4.000e+04 7.609e-04 2.847e-05 -29.58° -203.78°
5 5.000e+04 3.966e-04 1.484e-05 -94.52° -268.72°
6 6.000e+04 2.910e-04 1.089e-05 158.48° -15.72°
7 7.000e+04 7.928e-04 2.967e-05 131.18° -43.02°
8 8.000e+04 2.310e-04 8.643e-06 137.23° -36.97°
9 9.000e+04 5.948e-04 2.226e-05 -173.89° -348.10°
10 1.000e+05 2.767e-04 1.035e-05 147.85° -26.35°
Total Harmonic Distortion: 0.016836%

sodfa_class_d_001 THD

Per .tran options, skipping operating point for transient analysis.
Changing Tseed to 1e-010
Changing Tseed to 1e-012
Heightened Def Con from 5.52581e-005 to 5.52631e-005
Heightened Def Con from 0.000486508 to 0.000486513
Fourier components of V(output)
DC component:-0.0286258

Harmonic Frequency Fourier Normalized Phase Normalized
Number [Hz] Component Component [degree] Phase [deg]
1 1.000e+04 2.645e+01 1.000e+00 167.79° 0.00°
2 2.000e+04 3.672e-03 1.388e-04 -97.61° -265.40°
3 3.000e+04 1.136e-02 4.294e-04 -56.04° -223.83°
4 4.000e+04 2.805e-03 1.060e-04 -76.36° -244.15°
5 5.000e+04 8.415e-04 3.181e-05 140.66° -27.12°
6 6.000e+04 3.277e-03 1.239e-04 -108.79° -276.58°
7 7.000e+04 3.673e-03 1.388e-04 -88.74° -256.53°
8 8.000e+04 4.050e-03 1.531e-04 -102.67° -270.45°
9 9.000e+04 3.128e-03 1.182e-04 -70.75° -238.54°
10 1.000e+05 2.682e-03 1.014e-04 -78.02° -245.80°
Total Harmonic Distortion: 0.054611%

Obviously my preference is the UcD as it simulates a lot better and uses fewer components also, and I usually keep with my motto 'keep it simple'.

Best regards,

Sander Sassen
http://www.hardwareanalysis.com