19.02.2009, 07:25 PM
hat evtl. jemand ein modell für den tl494?
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tl494 modell?
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19.02.2009, 10:17 PM
Hallo sunny,
hier ist ein (ungeprüftes) Modell für den SG1524B aus der Pspice-Library. Der TL494 ist zumindest sehr ähnlich, so dass Du mit einigen kleineren Modifikationen zum Ziel kommen solltest. Einschränkung: Dieses Modell funktioniert nur zusammen mit der Vollversion von Pspice (ab Vers. 6), also dem Mixed-Mode Simulator (reiner Analog-Sim reicht nicht). Keine Ahnung, inwiefern das mit LTspice geht...
*** SG1524B ***
* The following model for the 1524B was obtained by consulting the data sheets
* and corresponding with Silicon General. A number of simplifications were
* made to speed up the model, among these we have:
* (a) replaced th oscillator with ideal voltage sources,
* (b) simplified the output stage (only two bipolars per output driver),
* © made the shutdown pin respond to digital stimulus, and
* (d) used digital simulation for the internal logic.
* The impact of that these simplifications must be considered in the context
* of the parameters of the circuit, and the circuit being examined. The
* above list might change as we get feedback.
.subckt SG1524B ; note: the node numbers are equivalent to chip pinout
+ 1 ; - input of error amp
+ 2 ; + input of error amp
+ 3 ; oscillator output
+ 4 ; + current loop sense
+ 5 ; - current loop sense
+ 7 ; oscillator ramp output, capacitor NOT NECESSARY due to (a) above.
+ 8 ; ground
+ 9 ; compensation pin
+ 10 ; shutdown pin
+ 11 ; emitter A
+ 12 ; collector A
+ 13 ; collector B
+ 14 ; emitter B
+ 15 ; vin
+ 16 ; vref
+ params:
+ period = 1ms ; internal clock period
+ deadtime = 1us ; internal clock deadtime
* Pin 6 (RT pin) NOT NECESSARY due to (a) above.
xdigpwr 8 DPWR DGND DIGIFPWR
xbufpwr 8 bufpwr bufgnd digifpwr params: voltage=5.7v
rextcl1 4 15 6.7meg
rextcl2 5 15 6.7meg
* stanby current
gp 15 DGND table {v(15)} (0 0) (6 5m)
v_clkset 7 DGND pulse(1 3 .1ns
+ {period-deadtime-2*deadtime/100} {deadtime} {deadtime/100} {period} )
u99 BUF bufPWR DGND dclk 3 d0_gate io_std
x15 7 dclk DPWR DGND gen_clk
* current limit section
ecurlim 909 DGND table {((v(4)-.2)-v(5))*1200} (0 0) (5 5)
rlim 909 911 43k
qclim 9 911 DGND q_pwm
rext 16 0 1G
rout 116 16 1
e18 116 0 table={v(15)} (0 0) (6 5)
x91 116 55 DPWR DGND uvsch
sreset1 9 DGND 55 DGND sreset
.model sreset vswitch (ron=500 roff=100meg von=2 voff=1.9)
x6 1 2 9 DPWR DGND erramp
o6 9 7 compmod dgtlnet=39 io_std
.model compmod doutput(
+ s0name=0 s0vlo=-15 s0vhi=0
+ s1name=1 s1vlo= 0 s1vhi=7 )
un1 and(2) DPWR DGND 510 39 4110 d0_gate io_std
uinv inv DPWR DGND 10 510 dshutd io_std
uinvd1 inv DPWR DGND 4110 4113 delgate io_std ; organizes the delay through cl
uinvd2 inv DPWR DGND 4113 40 delgate io_std ; comparator
.model dshutd ugate(tplhty=100ns, tphlty=100ns)
.model delgate ugate(tplhty= 62ns, tphlty= 62ns)
eintern 115 0 15 0 1
x1 115 dclk 40 31 32 DPWR DGND log1524b
x2 31 32 12 13 11 14 DPWR DGND ppout
.ends
______________________________________________________________________
Und ab hier noch eine Testschaltung mit dem SG1524B, auch aus der Pspice-Lib (Sterne und Striche müssen natürlich noch entfernt werden):
*+----------------------------------------------------------------------------
*|* POWER SUPPLY CONTAINING SG1524B
*|*
*|* THE FOLLOWING LINES CONFIGURE A BUCK REGULATOR AROUND A 1524B
*|* AND DEMONSTRATES THE USE OF THE 1524B MACROMODEL.
*|
*|.LIB "swit_reg.lib"
*|.LIB "digital.lib"
*|
*|.IC V(711)=4.8 ; INITIALIZE THE OUTPUT TO 5 VOLTS
*| ; (CLOSE TO STEADY)
*|
*|VIN 15 0 20 ; INPUT VOLTAGE SET TO 15 VOLTS
*|RLOAD 711 0 5 ; 1.25A LOAD CURRENT AT OUTPUT
*|UPRS STIM(1,1) $G_DPWR $G_8 10 IO_STM 0S 0 ; DIGITAL SHUTDOWN
*| ; SIGNAL DISABLED
*|VEMMITS EMMITS 0 0 ; TIE THE EMITTERS OF THE OUTPUT DRIVERS
*| ; TO GND
*|VREF 2 0 2.5 ; REFERENCE INPUT TO +IN OF ERROR AMP
*|X8 12 711 1 15 BUCK ; CALL TO BUCK CCT
*|V4 4 0 PULSE(0 1 6MS 1U 1U 1M 1) ; CURRENT OVERLOAD
*| ; SHUTDOWN TEST
*|VCLIM 5 0 0 ; -IN OF CURRENT LIMIT AMP GNDED
*|RCOMP 50 0 20K ; COMPENSATION RESISTOR
*|CCOMP 9 50 100N ; COMPENSATION CAPACITANCE
*|
*|X1 1 2 3 4 5 7 0 9 10 EMMITS 12 12 EMMITS 15 16 SG1524B
*|+ PARAMS: PERIOD=22U DEADTIME=0.5U
*|
*|* BUCK CONVERTER
*|.SUBCKT BUCK 7 5 21 1
*|R1 2 7 150
*|Q1 4 2 1 QX2
*|C1 5 88 4840UF
*|RZERO 88 0 .0002
*|RSNUB 4 5 1.5K
*|L1 4 5 500UH
*|D1 0 4 DX
*|RO1 5 21 10
*|RO2 21 0 10
*|.ENDS
*|
*|.MODEL DX D(IS=0.1P RS=16 CJO=2P TT=12N BV=100 IBV=0.1P)
*|.MODEL QX2 PNP(IS=1.34F XTI=3 EG=1.11 VAF=74.03 BF=65.62 NE=1.208
*|+ ISE=19.48F IKF=5.385 XTB=1.5 BR=9.715 NC=2 ISC=0 IKR=0 RC=1
*|+ CJC=1.393P MJC=.3416 VJC=.75 FC=.5 CJE=2.01P MJE=.377 VJE=.75
*|+ TR=.1N TF=408.8P ITF=.6 VTF=1.7 XTF=3 RB=10)
*|
*|.TRAN 10U 5MS
*|.PROBE V(711) V(1) I(L1) V(7) D(3) V(12) V(10) V(4)
*|.END
Grüßle vom Rumzucker
hier ist ein (ungeprüftes) Modell für den SG1524B aus der Pspice-Library. Der TL494 ist zumindest sehr ähnlich, so dass Du mit einigen kleineren Modifikationen zum Ziel kommen solltest. Einschränkung: Dieses Modell funktioniert nur zusammen mit der Vollversion von Pspice (ab Vers. 6), also dem Mixed-Mode Simulator (reiner Analog-Sim reicht nicht). Keine Ahnung, inwiefern das mit LTspice geht...
*** SG1524B ***
* The following model for the 1524B was obtained by consulting the data sheets
* and corresponding with Silicon General. A number of simplifications were
* made to speed up the model, among these we have:
* (a) replaced th oscillator with ideal voltage sources,
* (b) simplified the output stage (only two bipolars per output driver),
* © made the shutdown pin respond to digital stimulus, and
* (d) used digital simulation for the internal logic.
* The impact of that these simplifications must be considered in the context
* of the parameters of the circuit, and the circuit being examined. The
* above list might change as we get feedback.
.subckt SG1524B ; note: the node numbers are equivalent to chip pinout
+ 1 ; - input of error amp
+ 2 ; + input of error amp
+ 3 ; oscillator output
+ 4 ; + current loop sense
+ 5 ; - current loop sense
+ 7 ; oscillator ramp output, capacitor NOT NECESSARY due to (a) above.
+ 8 ; ground
+ 9 ; compensation pin
+ 10 ; shutdown pin
+ 11 ; emitter A
+ 12 ; collector A
+ 13 ; collector B
+ 14 ; emitter B
+ 15 ; vin
+ 16 ; vref
+ params:
+ period = 1ms ; internal clock period
+ deadtime = 1us ; internal clock deadtime
* Pin 6 (RT pin) NOT NECESSARY due to (a) above.
xdigpwr 8 DPWR DGND DIGIFPWR
xbufpwr 8 bufpwr bufgnd digifpwr params: voltage=5.7v
rextcl1 4 15 6.7meg
rextcl2 5 15 6.7meg
* stanby current
gp 15 DGND table {v(15)} (0 0) (6 5m)
v_clkset 7 DGND pulse(1 3 .1ns
+ {period-deadtime-2*deadtime/100} {deadtime} {deadtime/100} {period} )
u99 BUF bufPWR DGND dclk 3 d0_gate io_std
x15 7 dclk DPWR DGND gen_clk
* current limit section
ecurlim 909 DGND table {((v(4)-.2)-v(5))*1200} (0 0) (5 5)
rlim 909 911 43k
qclim 9 911 DGND q_pwm
rext 16 0 1G
rout 116 16 1
e18 116 0 table={v(15)} (0 0) (6 5)
x91 116 55 DPWR DGND uvsch
sreset1 9 DGND 55 DGND sreset
.model sreset vswitch (ron=500 roff=100meg von=2 voff=1.9)
x6 1 2 9 DPWR DGND erramp
o6 9 7 compmod dgtlnet=39 io_std
.model compmod doutput(
+ s0name=0 s0vlo=-15 s0vhi=0
+ s1name=1 s1vlo= 0 s1vhi=7 )
un1 and(2) DPWR DGND 510 39 4110 d0_gate io_std
uinv inv DPWR DGND 10 510 dshutd io_std
uinvd1 inv DPWR DGND 4110 4113 delgate io_std ; organizes the delay through cl
uinvd2 inv DPWR DGND 4113 40 delgate io_std ; comparator
.model dshutd ugate(tplhty=100ns, tphlty=100ns)
.model delgate ugate(tplhty= 62ns, tphlty= 62ns)
eintern 115 0 15 0 1
x1 115 dclk 40 31 32 DPWR DGND log1524b
x2 31 32 12 13 11 14 DPWR DGND ppout
.ends
______________________________________________________________________
Und ab hier noch eine Testschaltung mit dem SG1524B, auch aus der Pspice-Lib (Sterne und Striche müssen natürlich noch entfernt werden):
*+----------------------------------------------------------------------------
*|* POWER SUPPLY CONTAINING SG1524B
*|*
*|* THE FOLLOWING LINES CONFIGURE A BUCK REGULATOR AROUND A 1524B
*|* AND DEMONSTRATES THE USE OF THE 1524B MACROMODEL.
*|
*|.LIB "swit_reg.lib"
*|.LIB "digital.lib"
*|
*|.IC V(711)=4.8 ; INITIALIZE THE OUTPUT TO 5 VOLTS
*| ; (CLOSE TO STEADY)
*|
*|VIN 15 0 20 ; INPUT VOLTAGE SET TO 15 VOLTS
*|RLOAD 711 0 5 ; 1.25A LOAD CURRENT AT OUTPUT
*|UPRS STIM(1,1) $G_DPWR $G_8 10 IO_STM 0S 0 ; DIGITAL SHUTDOWN
*| ; SIGNAL DISABLED
*|VEMMITS EMMITS 0 0 ; TIE THE EMITTERS OF THE OUTPUT DRIVERS
*| ; TO GND
*|VREF 2 0 2.5 ; REFERENCE INPUT TO +IN OF ERROR AMP
*|X8 12 711 1 15 BUCK ; CALL TO BUCK CCT
*|V4 4 0 PULSE(0 1 6MS 1U 1U 1M 1) ; CURRENT OVERLOAD
*| ; SHUTDOWN TEST
*|VCLIM 5 0 0 ; -IN OF CURRENT LIMIT AMP GNDED
*|RCOMP 50 0 20K ; COMPENSATION RESISTOR
*|CCOMP 9 50 100N ; COMPENSATION CAPACITANCE
*|
*|X1 1 2 3 4 5 7 0 9 10 EMMITS 12 12 EMMITS 15 16 SG1524B
*|+ PARAMS: PERIOD=22U DEADTIME=0.5U
*|
*|* BUCK CONVERTER
*|.SUBCKT BUCK 7 5 21 1
*|R1 2 7 150
*|Q1 4 2 1 QX2
*|C1 5 88 4840UF
*|RZERO 88 0 .0002
*|RSNUB 4 5 1.5K
*|L1 4 5 500UH
*|D1 0 4 DX
*|RO1 5 21 10
*|RO2 21 0 10
*|.ENDS
*|
*|.MODEL DX D(IS=0.1P RS=16 CJO=2P TT=12N BV=100 IBV=0.1P)
*|.MODEL QX2 PNP(IS=1.34F XTI=3 EG=1.11 VAF=74.03 BF=65.62 NE=1.208
*|+ ISE=19.48F IKF=5.385 XTB=1.5 BR=9.715 NC=2 ISC=0 IKR=0 RC=1
*|+ CJC=1.393P MJC=.3416 VJC=.75 FC=.5 CJE=2.01P MJE=.377 VJE=.75
*|+ TR=.1N TF=408.8P ITF=.6 VTF=1.7 XTF=3 RB=10)
*|
*|.TRAN 10U 5MS
*|.PROBE V(711) V(1) I(L1) V(7) D(3) V(12) V(10) V(4)
*|.END
Grüßle vom Rumzucker
20.02.2009, 05:32 PM
dank dir! es funktioniert aber leider nicht im lt-spice. ich hab aber mittlerweile eins gefunden. es hat sich also erst mal erledigt.